1. Field of the Invention
This invention relates to an opaque cover for preventing light from reaching the floating gate of a floating gate transistor.
Floating gate memory devices such as EPROMs are well known in the art. Such devices typically include an array of floating gate transistors for storing data. Unfortunately, some of the transistors within the array are sometimes defective. Accordingly, it is known in the art to manufacture EPROMs using redundant memory cells. Thus, if the EPROM includes a defective memory cell, the defective memory cell is decoupled from the array and a redundant cell is coupled to the array to replace the defective cell.
It is known in the art to provide an extra floating gate transistor in the EPROM to programmably control whether the redundant cells are to be coupled to the array to replace defective cells. Of importance, the extra floating gate transistor can be programmed to couple the redundant cells to the array but an opaque metal cover is formed over the extra transistor to prevent it from being erased when the rest of the EPROM is exposed to UV light. An example of such a structure is discussed in the article entitled "PROM Cell Made With An EPROM Process" by Alan C. Folmsbee, published at the International Electron Devices Meeting in 1983, incorporated herein by reference.
FIG. 1 illustrates in cross-section the Folmsbee structure, in which a metal cover 1 is formed over a floating gate transistor 2. Floating gate transistor 2 comprises a drain 3, a source 4, a floating gate 5 and a control gate 6. A thick oxide layer 9 is formed between floating gate transistor 2 and metal cover 1 to electrically insulate metal cover 1 from floating gate 6, drain 3, and the semiconductor substrate. Metal cover 1 reflects ambient light 7, and thereby prevents the light from reaching floating gate 5. Folmsbee provides an opening 8 in metal cover 1 so that portions of the drain 3 and control gate 6 can extend outside of the metal cover 1 where they can be electrically contacted.
Folmsbee's structure has a number of problems. light can enter through opening 8 in metal cover 1. This light reflects off of silicon substrate 10 and metal cover 1 and is attenuated when it reaches floating gate 5. To ensure that the light is sufficiently attenuated by the time it reaches floating gate 5, it is necessary to either minimize the thickness T.sub.OX of oxide layer 9 or increase the distance D between transistor 2 and opening 8. Unfortunately, it is difficult to minimize oxide thickness T.sub.OX underneath metal cover 1 because conventional semiconductor processes used to manufacture EPROMs do not typically include a step which allows for the formation of a thin oxide layer between the metallization and the underlying semiconductor substrate. Instead, such processes typically require the formation of a thick oxide layer between the metallization and underlying substrate so that the likelihood of a short circuit between the metallization and the substrate is reduced. Thus, instead of minimizing thickness T.sub.OX of oxide layer 9, Folmsbee uses an oxide thickness of 1.85 microns, and must increase the size of metal cover 1 so that distance D is 80 microns. Therefore, Folmsbee's structure takes up a large surface area and is expensive to build.
Another problem with the structure of FIG. 1 is that most EPROMs are constructed using a single layer of interconnect metallization. By using the metal layer to form cover 1, it is impossible to extend metal interconnects over opaque cover 1 in most EPROM processes. Because metal interconnects cannot be placed over metal cover 1, the surface area of the integrated circuit cannot be used as efficiently as it could if one could pass metal interconnects over the opaque cover.
U.S. Pat. No. 4,519,050, issued on May 21, 1985 to Folmsbee, discusses a structure similar to the structure described in the above-cited Folmsbee paper and, thus, suffers from the shortcomings of the structure of FIG. 1.